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1 (15) da6181b.002 5 may, 2011 MAS6181B am receiver ic ? dual band receiver ic ? high sensitivity ? very low power consumption ? wide supply voltage range ? power down control ? control for agc on ? high selectivity by crystal filter ? fast startup feature description the mas6181 am-receiver chip is a highly sensitive, simple to use am receiver specially intended to receive time signals in the frequency range from 40 khz to 100 khz. only a few external components are required for time signal receiving. the circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. the output signal can be processed directly by an additional digital circuitry to extract the data fr om the received signal. the control for agc (automatic gai n control) can be used to switch agc on or off if necessary. the mas6181 supports receiving two different frequency signals by two selective crystal filters and an integrated switch to switch between two antenna frequencies. it has differential input for improved common mode disturbance rejection. features applications ? dual band receiver ic ? highly sensitive am receiver ? wide supply voltage range from 1.1 v to 3.6 v ? very low power consumption ? power down control ? fast startup ? only a few external components necessary ? control for agc on ? wide frequency range from 40 khz to 100 khz ? high selectivity by quartz crystal filter ? differential input ? multi band time signal receiver wwvb (usa), jjy (japan), dcf77 (germany), msf (uk), hbg (switzerland) and bpc (china) block diagram agc amplifier power supply/biasing demodulator & comparator rfim rfi2 vdd vss pdn1 agc dec out qi aon qo1 qo2 pdn2 rfip vdd vdd
2 (15) da6181b.002 5 may, 2011 pad layout 1530 ? m 1120 ? m MAS6181B1 vdd qo2 qo1 qi agc pdn2 out vss rfi2 rfim rfip pdn1 aon dec 1st bond! rfimb rfi2b do not bond! die size = 1120 x 1530 m; rectangular pad 80 m x 80 m note: because the substrate of the die is internally conn ected to vss, the die has to be connected to vss or left floating. please make sure that vss is the first pa d to be bonded. pick-and-place and all component as sembly are recommended to be performed in esd protected ar ea. note: coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. pad identification name x-coordinate y-coordinate n ote power supply voltage vdd 126 m 1332 m quartz filter output for crystal 2 qo2 126 m 1132 m quartz filter output for crystal 1 qo1 126 m 962 m quartz filter input for crystals qi 126 m 788 m agc capacitor agc 126 m 614 m power down/frequency selection input 2 pdn2 126 m 440 m 1 receiver output out 126 m 263 m 2 demodulator capacitor dec 994 m 266 m agc on control aon 994 m 450 m 3 power down/frequency selection input 1 pdn1 994 m 618 m 1 positive receiver input rfip 994 m 807 m 4 negative receiver input rfim 994 m 985 m 4 test pad rfimb rfimb 298 m 1025 m 5 test pad rfi2b rfi2b 400 m 1025 m 5 receiver input 2 (for antenna capacitor 2) rfi2 994 m 1163 m power supply ground vss 994 m 1321 m notes: 1) pdn1 = vdd and pdn2 = vdd means receiver off - fast start-up is triggered when the receiver is af ter power down controlled to power on 2) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 3) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (normal operation) - unused aon pad can be left unconnected due to inte rnal pull-up with current < 1 a. pull up current is switched off at power down. 4) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd 5) rfimb and rfi2b pads are left unconnected. they are only for wafer level testing purposes
3 (15) da6181b.002 5 may, 2011 absolute maximum ratings parameter symbol conditions min max unit supply voltage v dd -v ss -0.3 3.6 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t op -40 +85 o c storage temperature t st -55 +150 o c stresses beyond those listed may cause permanent da mage to the device. the device may not operate unde r these conditions, but it will not be destroyed. electrical characteristics operating conditions: vdd = 1.5v, temperature = 27 c unless otherwise noted parameter symbol conditions min typ max unit operating voltage v dd 1.10 1.5 3.6 v current consumption i dd vdd=1.5 v, vin=0 vrms vdd=1.5 v, vin=20 mvrms vdd=3.6 v, vin=0 vrms vdd=3.6 v, vin=20 mvrms 31 24 66 40 68 42 85 65 a stand-by current i ddoff 0.1 a input frequency range f in 40 100 khz minimum input voltage v in min 0.4 1 vrms maximum input voltage v in max 20 mvrms receiver input resistance receiver input capacitance r rfi c rfi f=40khz...77.5 khz 600 1.1 k pf rfi2 switch on resistance rfi2 switch off capacitance r on2 c off2 vdd=1.4 v 5 20 15 pf input levels |l in |<0.5 a v il v ih v dd -0.35 0.35 v output current v ol <0.2 v dd ;v oh >0.8 v dd |i out | 5 a dcf77 output pulses t 100ms t 20 0ms 1 vrms v in 20 mvrms, see note below! 95 195 ms msf output pulses t 100ms t 200ms t 300ms t 5 00ms 1 vrms v in 20 mvrms, see note below! 120 220 320 520 ms wwvb output pulses t 200ms t 500ms t 8 00ms 1 vrms v in 20 mvrms, see note below! 200 500 800 ms jjy60 output pulses t 200ms t 500ms t 8 00ms 1 vrms v in 20 mvrms, see note below! 210 505 800 ms jjy40 output pulses t 200ms t 500ms t 8 00ms 1 vrms v in 20 mvrms, see note below! 200 495 790 ms startup time t start fast start-up, vin=0.4 vrms fast start-up, vin=20 mvrms 1.3 3.5 s output delay time t delay 50 100 ms note: stand-by current consumption may increase if v ih and v il differ from vdd and gnd respectively. note: see note 6: time signal software?s pulse width rec ognition limits and table 5 on page 9!
4 (15) da6181b.002 5 may, 2011 frequency selection the power down control and frequency selection using internal antenna?s tuning capacitor switch (rfi2) are achieved by two digital control pins pdn1 and pdn2. the control logic is presented in table 1. table 1. frequency selection and power down control pdn1 pdn2 rfi2 switch description high high open power down high low open antenna frequency 1 low high closed antenna frequency 2, rfi2 capacitor connected in parallel with antenna low low closed antenna frequency 2, rfi2 capacitor connected in parallel with antenna if frequency 1 is selected the rfi2 switch is open (non conductive). antenna frequency is determined by antenna inductor l ant (see typical application on page 5), antenna capacitor c ant1 and parasitic capacitances related to antenna coil, inputs rfip, rfim and rfi2 (see antenna tuning considerations below). frequency 1 is the highest frequency of the two selected frequencies. if frequency 2 is selected then rfi2 switch is clos ed to connect c ant2 to pin rfim in parallel with ferrite antenna and tune it to frequency 2. frequency 2 is the lowest frequency of the two selected frequencies. it is recommended to switch the device to power down for at least 50ms before switching to another frequency. this guarantees fast startup in switchin g to another frequency. during minimum 50ms power down time the agc capacitor voltage is completely pulled to vdd to initialize proper startup conditio ns for the agc. without the described proper fast startup control the startup time can be several minutes. with fast startup it is shortened typicall y to a few seconds. antenna tuning considerations the ferrite bar antenna having inductance l ant and parasitic coil capacitance c coil is tuned to two reception frequencies f 1 and f 2 by parallel capacitors c ant1 and c ant2 . the receiver input stage and internal antenna capacitor switches have capacitances c rfi and c off2 which affect the resonance frequencies. c off2 is switch capacitance when switch is open. when the antenna switch is closed the off capacitance is shorted by on resistance of the switch and it is effectively eliminated. following relationships can be written for the two tuning frequencies. frequency f 1 (highest frequency): c tot1 ~c coil +c ant1 +c rfi +c off2 , assuming c ant2 >>c off2 1 1 2 1 tot ant c l f ? = frequency f 2 (lowest frequency): c tot2 =c coil +c ant1 +c ant2 +c rfi 2 2 2 1 tot ant c l f ? =
5 (15) da6181b.002 5 may, 2011 typical application v battery receiver output power down / fast startup / frequency selection optional control for agc on/hold x 1 x 2 ferrite antenna c ant1 c ant2 l ant note 1 agc amplifier power supply/biasing demodulator & comparator rfim rfi2 vdd vss pdn1 agc dec out qi aon qo1 qo2 pdn2 rfip vdd vdd c agc 10 ? f c dec 47 nf note 2 vdd vdd note 5 note 4 note 3 figure 1. application circuit of dual band receiver mas6181 v battery receiver output power down / fast startup / frequency selection optional control for agc on/hold x 2 40003 hz ferrite antenna c ant1 1.9 nf c ant1 2.4 nf l ant 3.64 mh note 1 agc amplifier power supply/biasing demodulator & comparator rfim rfi2 vdd vss pdn1 agc dec out qi aon qo1 qo2 pdn2 rfip vdd vdd c agc 10 ? f c dec 47 nf note 2 vdd vdd note 5 note 4 note 3 x 1 60003 hz figure 2. example circuit of dual band receiver mas6181 for j jy 60 khz and 40 khz frequencies
6 (15) da6181b.002 5 may, 2011 typical application (continued) receiver output power down / fast startup / frequency selection x1 x2 ferrite antenna c1 c2 l1 agc amplifier power supply/biasing demodulator & comparator rfim rfi2 vdd vss pdn1 agc dec out qi aon qo1 qo2 pdn2 rfip vdd vdd c agc 10 ? f c dec 47 nf vdd vdd c3 x3 cext~0.75pf 3rd antenna frequency selection vdd figure 3. application circuit of mas6181 in tri band receiver configuration
7 (15) da6181b.002 5 may, 2011 typical application (continued) note 1: crystals the crystals as well as ferrite antenna frequencies are chosen according to the time signal system (ta ble 2). the reason why the crystal frequency is about 3 hz higher than the signal frequency is that the crysta l is operated without the loading capacitor. without loa ding capacitor the actual resonance frequency is ab out 3 hz lower than with load thus 77.503 khz crystal resona tes at 77.500 khz when no loading capacitor is used . table 2. time signal system frequencies time signal system location antenna frequency recom mended crystal frequency dcf77 germany 77.5 khz 77.503 hz hbg switzerland 75 khz 75.003 khz msf united kingdom 60 khz 60.003 khz wwvb usa 60 khz 60.003 khz jjy japan 40 khz and 60 khz 40.003 khz and 60.003 k hz bpc china 68.5 khz 68.505 khz the parasitic shunt capacitance c 0 of the two crystals should be as similar to each o ther as possible since they are used to cancel each other. large shunt capacita nce mismatch between the two crystals can lead to n on- ideal filter characteristics and wide noise band-wi dth. effectively this means lower sensitivity perfo rmance. it should be noted that grounded crystal package ha s reduced shunt capacitance. this value is about 85 % of floating crystal shunt capacitance. for example cry stal with 1pf floating package shunt capacitance ca n have 0.85pf grounded package shunt capacitance. pcb trac es of crystal and external compensation capacitance should be kept at minimum to minimize additional pa rasitic capacitance which can cause capacitance mismatching. when using MAS6181B1 it does not matter which of th e two frequency crystals is connected to qo1 pin an d which to qo2 pin. table 3 below presents some crystal suppliers havin g suitable crystals for time signal receiver applic ation. table 3. crystal suppliers and crystal types in alphabetical order for time signal receiver application supplier crystal type dimensions web link citizen cfv-206 ? 2.0 x 6.0 http://www.citizen.co.j p/tokuhan/quartz/ epson toyocom c-2-type c-4-type ? 1.5 x 5.0 ? 2.0 x 6.0 http://www.epsontoyocom.co.jp/english/ kds daishinku dt-261 ? 2.0 x 6.0 http://www.kds.inf o/index_en.htm microcrystal ms3v-t1r 1.45 x 1.45 x 6.7 http://www. microcrystal.com/ seiko instruments vtc-120 ? 1.2 x 4.7 http://www.sii-crystal.com note 2: agc capacitor the 10 f agc and 47nf dec capacitors must have low leakage currents due to very small signal currents through the capacitors. the insulation resistance o f these capacitors should be at minimum several 100 m . also probes with at least several 100 m impedance should be used for voltage probing of the agc and dec pins to not disturb their operation. tantalum capac itors have lower leakage than the electrolyte capac itors. in case of using electrolyte type agc capacitor the ca pacitor voltage rating should be at least 25 v for sufficiently low leakage. the dec capacitor can be low leakage c hip capacitor since its capacitance value is small. it is recommended to connect both agc and dec capac itors to vdd (see application figures 1 and 2) alth ough vss connection is also possible. the vdd connection provides better supply noise immunity because the signals and agc gain are referenced to vdd. additio nally leakage currents are minimized in this connec tion because in power down the agc pin voltage is pulled to vdd (to minimum agc gain) providing zero voltag e over the agc capacitor.
8 (15) da6181b.002 5 may, 2011 typical application (continued) note 3: power down / fast startup control both power down and fast startup is controlled usin g the pdn pin. the device is in power down (turned off) if pdn1 = pdn2 = vdd and in power up with other three pdn1 and pdn2 control bit combinations (see table 1 on page 4). fast startup is triggered automatically wh en moving from power down to power up. the vdd must have been high before moving from power down to power up to guarantee proper operation of fast startup circ uitry. additionally the device should have been kept in po wer down state at least 50ms before power up. this guarantees that the agc capacitor voltage has been completely pulled to vdd during power down. the sta rtup time without proper fast startup control can be sev eral minutes. with fast startup it is shortened typ ically to a few seconds. note 4: optional control for agc on/hold aon control pin has internal pull up which turns ag c circuit on all the time if aon pin is left unconn ected. optionally aon control can be used to hold and rele ase agc circuit. stepper motor drive of analog cloc k or watch can produce disturbing amount of noise which can shift the input amplifier gain to non optimal l evel. this can be avoided by controlling agc hold (aon=vss) du ring stepper motor drive periods and releasing agc (aon=vdd) when motors are not driven. the agc shoul d be in hold only during disturbances and kept on o ther time released since due to leakage the agc can stil l change slowly when in hold. note 5: ferrite antenna the ferrite antenna converts the transmitted radio wave into a voltage signal. it has an important rol e in determining receiver performance. recommended anten na impedance at resonance is around 100 k . low antenna impedance corresponds to low noise but often also to small signal amplitude. on the other hand high antenna impedance corresponds to high noise bu t also large signal. the optimum performance where signal-to-noise ratio is at maximum is achieved in between. the antenna should have also some selectivity for r ejecting near signal band disturbances. this is det ermined by the antenna quality factor which should be appro ximately 100. much higher quality factor antennas s uffer from extensive tuning accuracy requirements and possible tuning drifts by the temperature. antenna impedance r ant can be calculated using equation 1 where f res , l, q ant and c are resonance frequency f res , coil inductance, antenna quality factor and anten na tuning capacitor respectively. antenna quality f actor q ant is defined by ratio of resonance frequency f res and antenna bandwidth b (equation 2). c b c f q q l f r res ant ant res ant ? ? = ? ? = ? ? ? = 2 1 2 2 equation 1. b f q res ant = equation 2. table 4 below presents some antenna suppliers for t ime signal application. table 4. antenna suppliers and antenna types in for time sig nal application supplier antenna type dimensions web link micro analog systems oy a10x60-77.5k222py a10x100-77.5k222py a3.5x4x15-7.87mh a2x3x21-0.92mh a3.75x3.75x23.6-0.92mh ? 10 x 60 mm ? 10 x 100 mm 3.5 x 4 x 15 mm 2 x 3 x 21 mm 3.75x3.75x23 mm http://www.mas- oy.com/en/products/radio-controlled- clock-rcc/antennas/ hr electronic gmbh 60716 (60 khz) 60708 (77.5 khz) ? 10 x 60 mm http://www.hrelectronic.com/ hitachi metals an-t702sxx an-t702mxx an-t702lxx 19 x 5.5 x 6.3 mm 28 x 5 x 5 mm 50 x 5 x 5 mm http://www.hitachi- metals.co.jp/e/prod/prod06/p06_12.html premo rca-smd-77a (77.5 khz) rca-smd-60a (60 khz) 75 x 15 x 6.3 mm http://www.grupopremo.com/ sumida acl80a (40 khz) ? 10 x 80 mm www.sumida.co.j p/jeita/xja021.pdf
9 (15) da6181b.002 5 may, 2011 typical application (continued) note 6: time signal software?s pulse width recognit ion limits the typical output pulse width specifications are p resented in the electrical characteristics section on page 3. due to process variations the typical output pulse width can differ from these. additionally the outpu t pulse widths can vary even more depending on the receivin g antenna signal strength versus noise and disturba nce conditions. that is why it is important that the ti me signal decoding software has appropriate toleran ce limits for managing the output pulse width variations successf ully. the table 5 presents recommended software pul se width tolerance limits for recognizing pulses of di fferent time signals. table 5. recommended software pulse width recognition limits for different time signals parameter symbol min max unit dcf77 output pulses t 100ms t 20 0ms 40 140 130 250 ms msf output pulses t 100ms t 200ms t 300ms t 5 00ms 50 170 280 400 160 270 380 600 ms wwvb output pulses t 200ms t 500ms t 8 00ms 100 400 700 300 600 900 ms jjy60 output pulses t 200ms t 500ms t 8 00ms 100 400 700 300 600 900 ms jjy40 output pulses t 200ms t 500ms t 8 00ms 100 400 700 300 600 900 ms
10 (15) da6181b.002 5 may, 2011 mas6181 samples in pdip-20 package 1 vdd 2 qo2 3 qo1 4 5 6 qi 7 agc 8 pdn2 9 out 10 20 vss 19 rfi2 18 rfim 17 rfip 16 15 14 pdn1 13 aon 12 dec 11 mas6181zz yyww xxxxx.x top marking definitions: yyww = year week xxxxx.x = lot number zz = sample version pin description pin name pin type function note 1 nc vdd 2 p positive power supply qo2 3 ao quartz filter output for crystal 2 qo1 4 ao quartz filter output for crystal 1 5 nc 1 6 nc 1 qi 7 ai quartz filter input for crystal agc 8 ao agc capacitor pdn2 9 di power down/frequency selection input 2 2 out 10 do receiver output 3 11 nc dec 12 ao demodulator capacitor aon 13 di agc on control 4 pdn1 14 di power down/frequency selection input 1 2 15 nc 16 nc rfip 17 ai positive receiver input 5 rfim 18 ai negative receiver input 5 rfi2 19 ai receiver input 2 (for antenna capacitor 2) vss 20 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) pins 5 and 6 between qo1 and qi must be connecte d to vss to eliminate dil package lead frame parasi tic capacitances disturbing the crystal filter performa nce. all other nc (not connected) pins are also recommended to be connected to vss to minimize nois e coupling. 2) pdn1 = vdd and pdn2 = vdd means receiver off - fast start-up is triggered when the receiver is af ter power down controlled to power on 3) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 4) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (normal operation) - unused aon pad can be left unconnected due to inte rnal pull-up with current < 1 a. pull up current is switched off at power down. 5) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd
11 (15) da6181b.002 5 may, 2011 pin configuration & top marking for plastic tssop-1 6 package qo2 vdd qo1 qi agc pdn2 out rfim vss rfi2 rfip pdn1 aon dec 6181bz yyww top marking definitions: z = version number yyww = year week pin description pin name pin type function note vdd 1 p positive power supply qo2 2 ao quartz filter output for crystal 2 qo1 3 ao quartz filter output for crystal 1 4 nc 1 qi 5 ai quartz filter input for crystal and externa l compensation capacitor agc 6 ao agc capacitor pdn2 7 di power down/frequency selection input 2 2 out 8 do receiver output 3 dec 9 ao demodulator capacitor aon 10 di agc on control 4 pdn1 11 di power down/frequency selection input 1 2 12 nc rfip 13 ai positive receiver input 5 rfim 14 ai negative receiver input 5 rfi2 15 ai receiver input 2 (for antenna capacitor 2) vss 16 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) pin 4 between qo1 and qi must be connected to vs s to eliminate tssop package lead frame parasitic capacitances disturbing the crystal filter performa nce. all other nc (not connected) pins are also recommended to be connected to vss to minimize nois e coupling. 2) pdn1 = vdd and pdn2 = vdd means receiver off - fast start-up is triggered when the receiver is af ter power down controlled to power on 3) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull do wn switch) 4) aon = vss means agc off (hold current gain level ); aon = vdd means agc on (normal operation) - unused aon pad can be left unconnected due to inte rnal pull-up with current < 1 a. pull up current is switched off at power down. 5) receiver inputs rfip and rfim have both 1.4 m biasing resistors towards vdd
12 (15) da6181b.002 5 may, 2011 package (tssop-16) outlines dimension min max unit a 6.40 bsc mm b 4.30 4.50 mm c 5.00 bsc mm d 0.05 0.15 mm e 1.10 mm f 0.19 0.30 mm g 0.65 bsc mm h 0.18 0.28 mm i 0.09 0.20 mm i1 0.09 0.16 mm j 0.19 0.30 mm j1 0.19 0.25 mm k 0 8 l 0.24 0.26 mm m (the length of a terminal for soldering to a substrate) 0.50 0.75 mm n 1.00 ref mm o 12 p 12 dimensions do not include mold flash, protrusions, or gate burrs. all dimensions are in accordance with jedec standar d mo-153. b a c pin 1 d seating plane e h g f b b detail a l k m n p o detail a i i1 j j1 section b-b
13 (15) da6181b.002 5 may, 2011 soldering information u for pb-free, rohs compliant tssop-16 resistance to soldering heat according to rsh test iec 68-2-58/20 maximum temperature 260 c maximum number of reflow cycles 3 reflow profile thermal profile parameters stated in ipc/jedec j-std-020 should not be exceeded. http://www.jedec.org seating plane co-planarity max 0.08 mm lead finish solder plate 7.62 - 25.4 m, material matte tin embossed tape specifications dimension min max unit a 0 6.50 6.70 mm b 0 5.20 5.40 mm d 0 1.50 +0.10 / -0.00 mm d 1 1.50 mm e 1 1.65 1.85 mm f 1 7.20 7.30 mm k 0 1.20 1.40 mm p 11.90 12.10 mm p 0 4.0 mm p 2 1.95 2.05 mm s 1 0.6 mm t 0.25 0.35 mm w 11.70 12.30 mm p 0 p p 2 a 0 d 1 d 0 a a section a - a e 1 f 1 w tape feed direction b 0 t k 0 s 1 tape feed direction pin 1 designator
14 (15) da6181b.002 5 may, 2011 reel specifications dimension min max unit a 330 mm b 1.5 mm c 12.80 13.50 mm d 20.2 mm n 50 mm w 1 (measured at hub) 12.4 14.4 mm w 2 (measured at hub) 18.4 mm trailer 160 mm leader 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm weight 1500 g d a b c n w 1 w 2 tape slot for tape start components trailer leader carrier tape cover tape start end 2000 components on each reel reel material: conductive, plastic antistatic or st atic dissipative carrier tape material: conductive cover tape material: static dissipative
15 (15) da6181b.002 5 may, 2011 ordering information product code product description MAS6181B1tc00 dual band am-receiver ic with differential input ews-tested wafer, diameter 8?, thickness 395 m 5%. MAS6181B1uc06 dual band am-receiver ic with differential input tssop-16, pb-free, rohs compliant, tape & reel contact micro analog systems oy for other wafer thi ckness options. u the formation of product code an example for MAS6181B1tc00: mas6181 b 1 tc 00 product name design version capacitance option: c c = 0.75 pf package type: tc = 400 m thick ews tested wafer delivery format: 00 = undiced wafer 05 = dies on tray 06 = tape & reel 08 = in tube local distributor micro analog systems oy contacts micro analog systems oy kutomotie 16 fi-00380 helsinki, finland tel. int. +358 10 835 1100 telefax +358 10 835 1119 http://www.mas-oy.com notice micro analog systems oy reserves the right to make changes to the products contained in this data shee t in order to improve the design or performance and to supply the best possible product s. micro analog systems oy assumes no responsibilit y for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specifi ed in this data sheet, and makes no claim that the circuits are free from patent infrin gement. applications for any devices shown in this data sheet are for illustration only and micro analog systems oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.

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